{
  "schema": "sync-camera-research-findings-v1",
  "researchDates": [
    "2026-09-18"
  ],
  "findings": [
    {
      "cycle": "A",
      "title": "GPU Fence Readiness and Pipelining",
      "finding": "Across both quiet baseline and 16-pass GPU load conditions, the GPU fence synchronization interval (fenceEndToFirstPollStart) required a median of 11.70 ms (quiet, p95: 12.60 ms) and 12.40 ms (load, p95: 13.10 ms). In 100% of evaluated submissions (1,200/1,200 per arm), the fence was ALREADY_SIGNALED upon the subsequent 16.67 ms animation frame poll, resulting in 0 not-ready fence polls and 0 frame drops. The GPU render-to-readback pipeline operates cleanly within a single-frame pipeline budget."
    },
    {
      "cycle": "B",
      "title": "Post-Fence Readback, Copy, and Send Overheads",
      "finding": "Once fence readiness is established, CPU walltime is dominated by WebGL2 PBO buffer readback and row-by-row vertical flipping (gl.getBufferSubData + 1,080 slice copies: median 3.30 ms, p95 3.90 ms). Subsequent Sync SDK staging payload copy (0.60 ms quiet / 0.20 ms load) and WebSocket socket.send invocation (0.80 ms quiet / 0.70 ms load) require an aggregate 1.50 ms (quiet) and 0.90 ms (load). Total elapsed time from frame timestamp to socket submission reaches median 20.70 ms (quiet) and 20.20 ms (load), explaining why previous unseparated traces observed ~20.3 ms stamp-to-send latency."
    },
    {
      "cycle": "C",
      "title": "DVFS Scaling Under Controlled GPU Workload",
      "finding": "Applying a 16-pass heavy GPU load increased M4 GPU active ratio from 0.65 to 0.79, GPU clock frequency from 345 MHz to 1,321 MHz, and total host power from 5.38 W to 9.44 W. Because Apple Silicon dynamic voltage and frequency scaling (DVFS) escalated GPU and memory subsystem clocks to maximum performance states under load, CPU readback and copy durations decreased slightly (payload copy p50 dropped from 0.60 ms to 0.20 ms; submit p50 dropped from 5.00 ms to 4.20 ms). The GPU readback bottleneck is governed by memory copy throughput and coordination rather than shader core contention."
    }
  ]
}