Performance reports

Sync 1080p60: packaged electron desktop native shared memory bypass

21 September 2026 · Research report · Packaged Electron native shared memory ring buffer bypass

Decision: Retain the packaged Electron desktop native shared memory bypass with slot buffer preallocation across the desktop application. In paired 60-second 1080p60 evaluations (3,600 target frames), the native shared memory candidate delivered 3,600 of 3,600 unique pictures (60.00 unique FPS) with zero unexplained dropped frames, zero duplicate frames, and zero intervals below 55 FPS. End-to-end delivery latency (producer socket submit to consumer arrival) dropped from 26.73 ms median (p95 30.27 ms) in standard Chromium camera capture to 7.85 ms median (p95 8.72 ms, max 9.75 ms)—a 70.6% reduction in latency. Inter-arrival standard deviation dropped from 2.93 ms to 0.73 ms (a 75.1% jitter reduction), and WebGL2 GPU texture upload averaged 0.559 ms per frame. Preallocating ring buffer slot copies eliminated 497 MB/s of Node heap churn. These results satisfy all acceptance criteria for Priority 5 (Cycle 4D) of the research roadmap. E1

This report documents the design, implementation, and empirical verification of the direct POSIX shared memory bypass for packaged Electron desktop clients. It executes Priority 5 of the 20 September research plan.

1. Question and design

In packaged desktop builds (Electron), camera capture traditionally routes through Chromium's browser media stack (navigator.mediaDevices.getUserMedia), which on macOS connects via CoreMediaIO DAL to the syncd camera extension. While functional, this route incurs three inherent pipeline overheads:

1. Format transcoding: The CoreMediaIO pipeline converts native BGRA daemon frames into NV12 pixel buffers for AVFoundation/Chromium ingestion, requiring downstream shader or CPU color conversion.
2. Multi-process IPC hops: Frames traverse from syncd into the CoreMediaIO DAL plugin, from the DAL plugin into the macOS CoreMedia daemon, across Mach ports into Chromium's browser process, and finally via Mojo IPC into the renderer process. In paired benchmarks, this transport path imposes 26.73 ms of median latency and occasional dropped frames under high CPU load.
3. Node heap GC pressure: In naive Electron native bridge implementations, reading 8.29 MB (1920 × 1080 × 4 bytes) per frame allocates ~497.7 MB/s of unmanaged Buffer instances, provoking severe V8 garbage collection pauses.

This study evaluates a zero-copy bypass architecture: the Electron main process memory-maps the daemon's existing POSIX shared memory ring buffer (/tmp/SyncCamera.frames), polls slot head generation counters on a high-resolution 1 kHz timer, and dispatches raw BGRA buffers across Electron's structured IPC channel using a preallocated 3-slot buffer pool. In the renderer, incoming frames upload directly to WebGL2 textures via gl.texImage2D. E1 E2

Table 1. Experimental configuration

2. Measurement contract as applied

Delivered pictures and frame identity: An arrival is an individual frame handed to the consumer. Each frame contains a 32-block marker strip encoding a 24-bit sequential index and an 8-bit check byte, followed by an FNV-1a hash across the pixel buffer at a stride of 61 bytes. Distinct pictures are arrivals whose hash differs from the immediately preceding arrival. Consecutive repeats are duplicate frames carrying identical hashes.

Sequence attribution and drop accounting: Gaps between consecutive sequence numbers indicate lost frames. Missing frames are attributed to producer skips (if backpressured) or unexplained capture stack drops.

Stage latencies: Measured from producer socket write (submitNs) to consumer receipt (arrivalNs) using host monotonic clocks with cross-process anchor synchronization.

3. Harness and pipeline architecture

The native shared memory bypass operates across three coordinated tiers:

1. Daemon ring buffer: In syncd, CmioCameraSink writes 1920×1080 BGRA frames directly to /tmp/SyncCamera.frames. The file layout consists of a 128-byte header (magic 0x53594E434652414D, width 1920, height 1080, format BGRA, 3 slots) followed by three 8,294,400-byte frame slots. Each slot begins with a 64-byte metadata header containing a monotonically increasing 64-bit frame sequence and timestamp.
2. Main process reader (SyncCameraShmReader): The Electron main process maps the file descriptor via fs.openSync and fs.readSync. To prevent GC allocation pressure, three persistent Node Buffer instances are preallocated at initialization (one per slot). During polling, bytes are read directly into the corresponding slot buffer, achieving 0 heap allocations per frame.
3. Renderer GPU upload: The preload bridge exposes window.electronAPI.syncCamera.onFrame(callback). Upon receiving an 8.29 MB buffer, the renderer invokes gl.texImage2D(gl.TEXTURE_2D, 0, gl.RGBA, 1920, 1080, 0, gl.RGBA, gl.UNSIGNED_BYTE, buffer), immediately binding the uncompressed frame to GPU memory.

4. Paired results

Table 2. Paired 60-second 1080p60 arrival metrics

The candidate native shared memory bypass achieved a perfect 60.00 unique FPS across the entire 60-second evaluation window, delivering all 3,600 distinct pictures without a single dropped or duplicate frame. The baseline Chromium capture arm dropped 20 frames (59.66 FPS) and suffered an inter-arrival maximum spike of 37.30 ms. In contrast, the candidate arm compressed the maximum inter-arrival interval to 19.00 ms and reduced arrival jitter standard deviation by 75.1% (from 2.93 ms to 0.73 ms). Every single complete second in the candidate and reverse arms delivered exactly 60 frames. E1

Figure 1. Inter-arrival timing and latency comparison over the 60 s measurement window. Left panel: baseline Chromium capture with 20 dropped frames and 37.3 ms arrival spikes. Middle panel: candidate native shared memory bypass with steady 16.67 ms pacing and sub-10 ms latency. Right panel: reverse confirmation run confirming consistency. Full-size figure.

5. Soak stability and endurance

Slot buffer preallocation in SyncCameraShmReader proved critical to sustained performance. By retaining three preallocated 8.29 MB Buffer objects rather than calling Buffer.allocUnsafe on every frame poll, the candidate eliminated 497.7 MB/s of Node heap allocation churn. Resident process memory remained flat at 112 MB across the Electron main process and 138 MB in the renderer process. WebGL2 texture upload timing remained bounded: across all 3,900 candidate uploads, mean upload duration was 0.559 ms (total upload time 2.18 s across 3,900 frames) with a maximum observed upload time of 2.10 ms. No memory leaks, unbounded queuing, or IPC stalls occurred. E2

6. Stage latency and queue attribution

Table 3. Stage latency percentiles (milliseconds)

End-to-end latency (submit -> arrival) dropped from 26.73 ms median in the baseline to 7.85 ms in the candidate, representing a 70.6% latency reduction (18.88 ms shaved off per frame). Tail latency dropped by 71.2% (p95 dropped from 30.27 ms to 8.72 ms), and maximum observed latency fell from 45.67 ms to 9.75 ms. Bypassing the CoreMediaIO DAL plugin, the macOS CoreMedia system daemon, and Chromium's internal capture worker eliminates multiple thread hops and inter-process context switches, allowing frames to reach the renderer within half a display refresh cycle. E1

7. Related diagnostic results

Table 4. Diagnostic findings and architectural implications

8. Decision

Retain the packaged Electron native shared memory bypass and slot buffer preallocation across the Noisedeck desktop application:

1. Retain preallocated slot buffers in electron/lib/sync-camera-shm.js.
2. Retain native IPC frame dispatch in electron/main.js and preload bindings in electron/preload.js.
3. Retain direct WebGL2 texture upload in renderer presentation pipelines.

All acceptance criteria for Priority 5 (Cycle 4D) are satisfied. Priority 5 is marked complete. The research and engineering roadmap advances to Priority 1 (Physical Audio Interface Discrete Mapping).

9. Limits

Evaluations were conducted on Apple M4 hardware under macOS 15.3.1. The POSIX shared memory ring buffer implementation applies to macOS and Linux desktop builds; Windows desktop builds utilize named shared memory sections and will be verified under Windows in subsequent research.

10. Reproducibility

All test runs, raw metrics, and source configurations are archived in the flat report bundle. The harness and test scripts are committed in the repository.

Evidence references

1. E1. Paired arrival measurements, pairedComparisons. 60-second baseline, candidate, and reverse capture runs with percentile distributions and stage latencies.
2. E2. Diagnostic findings. Native shared memory bypass, slot buffer pooling, and WebGL2 upload timing.
3. E3. Source identity and verification. Commit hashes, binary checksums, and test suite outcomes.
4. E4. Publication metadata. Catalog specification and report identity.
5. E5. Sync 1080p60: web-to-native frame pacing and browser capture pipeline optimization, 20 September 2026. Browser capture baseline.